Comparing the impact of power supply voltage on CMOS-and FinFET-based SRAMs in the presence of resistive defects

CMOS technology scaling has reached its limit at the 22 nm technology node due to several factors including Process Variations (PV), increased leakage current, Random Dopant Fluctuation (RDF), and mainly the Short-Channel Effect (SCE). In order to continue the miniaturization process via technology down-scaling while preserving system reliability and performance, Fin Field-Effect Transistors (FinFETs) arise as an alternative to CMOS transistors. In parallel, Static Random-Access Memories (SRAMs) increasingly occupy great part of Systems-on-Chips’ (SoCs) silicon area, making their reliability an important issue. SRAMs are designed to reach densities at the limit of the manufacturing process, making this component susceptible to manufacturing defects, including the resistive ones. Such defects may cause dynamic faults during the circuits’ lifetime, an important cause of test escape. Thus, the identification of the proper faulty behavior taking different operating conditions into account is considered crucial to guarantee the development of more suitable test methodologies. In this context, a comparison between the behavior of a 22 nm CMOS-based and a 20 nm FinFET-based SRAM in the presence of resistive defects is carried out considering different power supply voltages. In more detail, the behavior of defective cells operating under different power supply voltages has been investigated performing SPICE simulations. Results show that the power supply voltage plays an important role in the faulty behavior of both CMOS- and FinFET-based SRAM cells in the presence of resistive defects but demonstrate to be more expressive when considering the FinFET-based memories. Studying different operating temperatures, the results show an expressively higher occurrence of dynamic faults in FinFET-based SRAMs when compared to CMOS technology

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit’s permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics

Avaliação da confiabilidade de SRAM baseada em FinFET sob defeitos resistivos

The development of Fin Field Effect Transistor (FinFET) has made possible the continuous scaling-down of Complementary Metal-Oxide-Semiconductor (CMOS) technology, overcoming issues caused by the Short-Channel Effects. In parallel, the increasing need to store more and more information has resulted in the fact that Static Random-Access Memories (SRAMs) occupy a great part of integrated systems. Manufacturing process deviations have introduced different types of defects, strong and weak, that directly affect the SRAM’s reliability, causing different faults. One of the main factor that reduces the reliability and the lifetime of the FinFET-based SRAMs are the weak resistive defects. Weak resistive defects are considered the most important cause of test escapes, since opposing the strong resistive defects, that is easily detectable, weak defects require more than one consecutive operation for being propagated at logic level. In this context, this work investigates resistive defect implications on the reliability of FinFET-based SRAMs along with the combined effects of ionizing particle impacts in the SRAM transistors considering the presence of such resistive defects. Firstly, a study on functional implications regarding manufacturing resistive defects in FinFET-based SRAMs is presented. In more detail, a complete analysis of static and dynamic fault behavior is performed through electrical simulations of FinFET-based SRAMs considering different technological nodes. The results show that the sensitivity to this kind of defect is related to the size of technology, in which higher technological nodes are more sensitive to open defects and smaller technologies are sensitive to bridge defects. Secondly, a TCAD model of a FinFET-based SRAM cell was developed in order to allow the evaluation of cell sensitivity to ionizing particles causing Single Event Upsets (SEUs). In this part of the work was developed a new model representing ion strike in FinFET-based SRAM cells. Then, SPICE simulations were performed considering the current pulse parameters obtained with TCAD. Finally, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects may have either a positive or negative influence on the cell reliability, depending on the position where it is, against SEUs caused by ionizing particles.O desenvolvimento do Fin Field Effect Transistor (FinFET) tornou possível a redução contínua da tecnologia Complementary Metal-Oxide-Semiconductor (CMOS), contornando os problemas causados pelos efeitos de canal curto. Paralelamente, a crescente necessidade de armazenar grande quantidade de informação resultou no fato de que Static Random-Access Memories (SRAM) ocupam grande parte dos sitemas integrados. A variabilidade dos processos de fabricação pode causar vários tipos de defeitos, fortes e fracos, que afetam diretamente a confiabilidade de SRAMs, propagando diferentes tipos de falhas. Um dos principais fatores que reduzem a confiabilidade e a vida útil das SRAMs baseadas em FinFET são os defeitos resistivos fracos. Os defeitos resistivos fracos são considerados a causa mais importante de "test escape", pois ao contrário dos defeitos resistivos fortes, que são facilmente detectáveis, os defeitos fracos requerem mais de uma operação consecutiva para serem propagados em nível lógico Neste contexto, além da investigação dos defeitos resistivos fracos, este trabalho propõe investigar os efeitos de impacto de partículas ionizantes na confiabilidade de SRAMs baseadas em FinFET na presença destes defeitos. Primeiramente, é apresentado um estudo das implicações funcionais de defeitos resistivos de manufatura em SRAMs baseadas em FinFET. Mais detalhadamente, uma análise completa do comportamento de falha estática e dinâmica é realizada por meio de simulações elétricas em um bloco de memória SRAM baseado em tecnologia FinFET, considerando diferentes nós tecnológicos. Os resultados mostram que o grau de sensibilidade ao tipo de defeito está relacionado ao tamanho da tecnologia, sendo que nodos tecnológicos maiores são mais sensíveis a defeitos de circuito aberto (open) e tecnologias menores são mais sensíveis a defeitos de curto circuito (bridges). Posteriormente, um modelo TCAD de uma célula SRAM baseada em FinFET foi desenvolvido para permitir a avaliação do impacto de partículas ionizantes que causam o Single Event Upsets (SEUs). Nesta parte do trabalho, foi desenvolvido um novo modelo de curva para a representar o ataque iônico em células SRAM baseadas em FinFET. Em seguida, foram realizadas simulações SPICE considerando os parâmetros do pulso de corrente obtidos com o simulador TCAD. Finalmente, defeitos resistivos fracos foram injetados na célula SRAM baseada em FinFET. Os resultados mostram que defeitos fracos podem ter uma influência positiva ou negativa na confiabilidade das células contra SEUs causados por impacto de partículas ionizantes

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit’s permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics

The surgical safety checklist and patient outcomes after surgery: a prospective observational cohort study, systematic review and meta-analysis

© 2017 British Journal of Anaesthesia Background: The surgical safety checklist is widely used to improve the quality of perioperative care. However, clinicians continue to debate the clinical effectiveness of this tool. Methods: Prospective analysis of data from the International Surgical Outcomes Study (ISOS), an international observational study of elective in-patient surgery, accompanied by a systematic review and meta-analysis of published literature. The exposure was surgical safety checklist use. The primary outcome was in-hospital mortality and the secondary outcome was postoperative complications. In the ISOS cohort, a multivariable multi-level generalized linear model was used to test associations. To further contextualise these findings, we included the results from the ISOS cohort in a meta-analysis. Results are reported as odds ratios (OR) with 95% confidence intervals. Results: We included 44 814 patients from 497 hospitals in 27 countries in the ISOS analysis. There were 40 245 (89.8%) patients exposed to the checklist, whilst 7508 (16.8%) sustained ≥1 postoperative complications and 207 (0.5%) died before hospital discharge. Checklist exposure was associated with reduced mortality [odds ratio (OR) 0.49 (0.32–0.77); P\u3c0.01], but no difference in complication rates [OR 1.02 (0.88–1.19); P=0.75]. In a systematic review, we screened 3732 records and identified 11 eligible studies of 453 292 patients including the ISOS cohort. Checklist exposure was associated with both reduced postoperative mortality [OR 0.75 (0.62–0.92); P\u3c0.01; I2=87%] and reduced complication rates [OR 0.73 (0.61–0.88); P\u3c0.01; I2=89%). Conclusions: Patients exposed to a surgical safety checklist experience better postoperative outcomes, but this could simply reflect wider quality of care in hospitals where checklist use is routine